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cpri an d 10g ethernet data recovery ic with amp/eq from 614 .4 mbps to 10.3125 gbps data sheet ADN2905 rev. a document feedback information furnished by analog devices is believed to be accur ate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is grante d by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014 C 2016 analog devices, inc. all rights reserved. technical support www.analog.com features serial cpri data rates 61 4.4 m bps, 1.2288 gbps , 2.4576 gbps , 3.072 gbps , 4.9152 gbps , 6.144 gbps , and 9.8304 gbps ethernet data rates: 1.25 gbps and 10.3125 gbps no reference clock required jitter performance superior to the sff- 8431 jitter specif ications optional equalizer o r 0 db eq input mode quantizer s ensitivity: 200 mv p - p typical ( e qualizer m ode) sample phase adjust (5.65 gbps or greater) output polarity invert i 2 c to access optional features loss of lock (lol) indicator prbs generator/detec tor application aware powe r 349.5 mw at 9.8304 g bps , 0 db eq input mode 287.7 mw at 6. 144 g bps , 0 db eq input mode 249.3 mw at 3.072 g bps , 0 db eq input mode power s upply: 1.2 v , flexible 1.8 v to 3.3 v , and 3.3 v 4 mm 4 mm , 24 - lead lfcsp applications sff - 8431 - compatible ethernet: 10g e, 1g e , and cpri: os/l.6 up to os/l.96 general description the ADN2905 provides the receiver functions of quantization and multirate data recovery at 614.4 mbps, 1.2288 gbps, 1.25 gbps, 2.4576 gbps, 3.072 gbps, 4.9152 gbps, 6.144 gbps, 9.8304 gbps , and 10.3125 gbps, used in common public radio interface (cpri) and gigabit ethernet applications. t he adn290 5 automati cally locks to all the specified cpri and ethernet data rates without the need for an external reference clock or programming. the ADN2905 jitter performance exce eds the jitter requirement specified by sff - 8431 . the ADN2905 prov ides manual sample p hase adjustment . additionally, the user can select a n equalizer or a 0 db eq a s the input. the equalizer is either adaptive or can be manually set. the ADN2905 also supports pseudorandom binary sequence ( prbs ) generation, b it e rror dete ction, and input data rate read back features. the ADN2905 is available in a compact 4 mm 4 mm , 24- lead chip scale package (lfcsp) . all ADN2905 specifica tions are defined over the ambient temperature range of ?40c to +85c, unless otherwise noted. functional block dia gram i 2 c registers 0db eq v cc float v cm i 2 c i 2 c cml eq data input sampler sample phase adjust rxd txd clk ddr rxck frequency acquisition and lock detector fifo downsampler and loop filter phase shifter dco clock 2 n pin nin sck sda lol data rate refclkp/ refclkn (optional) datoutp/ datoutn ADN2905 2 50? 50? i 2 c_addr 12624-001 figure 1.
ADN2905 data sheet rev. a | page 2 of 27 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 jitter specifications ....................................................................... 4 output and timing specifications ............................................. 5 timing diagrams .......................................................................... 6 absolute maximum rating s ............................................................ 7 thermal characteristics .............................................................. 7 esd caution .................................................................................. 7 pin configuration an d function descriptions ............................. 8 typical performance characteristics ............................................. 9 i 2 c interface timing and internal register descriptions ......... 10 register map ............................................................................... 11 theory of operation ...................................................................... 15 functional description .................................................................. 17 frequency acquisition ............................................................... 17 edge select ................................................................................... 17 passive equalizer ........................................................................ 18 0 db eq ........................................................................................ 18 lock detector operation .......................................................... 18 harmonic detector .................................................................... 19 output disable and squelch ..................................................... 19 i 2 c interface ................................................................................ 20 reference clock (optional) ...................................................... 20 additional features available via the i 2 c interface ............... 22 input configurations ................................................................. 24 dc - coupled application .......................................................... 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision hi story 1 /1 6 rev 0. t o rev. a changes to figure 5 .......................................................................... 8 updated outline dimensions ....................................................... 27 changes to ordering guide .......................................................... 27 1 2 /1 4 revision 0 : initial version
data sheet ADN2905 rev. a | page 3 of 27 specifications t a = t min to t max , vcc = vcc min to vcc max , vcc1 = vcc1 min to vcc1 max , vdd = vdd min to vdd max , v ee = 0 v, i nput d ata p attern = prbs 2 23 ? 1 , ac - coupled (to 100 ? differential termination load ) , i 2 c register default settings, unless otherwise noted. table 1 . parameter test conditions/comments min typ max unit multi rate suppor t range 0.6144 10.3125 gbps input dc characteristics peak -to - peak differential input pin C nin , see figure 29 1.0 v input resistance differential 95 100 105 ? 0 db eq input cml compliant input v oltage range at pin or nin, dc - coupled, rx_term_float = 1 (float ed ) 0.5 vcc v input common - mode level dc - coupled (see figure 28 ), 600 mv p - p differential, rx_ term_float = 1 (float ed ) 0.65 vcc ? 0.15 v differential input sensit ivity cpri 16, 9.8304 gbps ac - coupled, rx_term_float = 0 (v cm = 1.2 v), bit error rate (ber) = 1 10 ?12 2 5 0 mv p -p equalizer input path differential input sensitivity 15 inch fr - 4, 100 ? differential transmission line, adaptive eq on cpri 16 , 9.8304 gbps ber = 1 10 ?1 2 200 mv p -p input ac characteristics s11 at 7.5 ghz, differential return loss, see figure 8 ?12 db loss of lock (lol) detect digital control oscillator ( dco ) frequency erro r for lol assert with respect to nominal, data collected in lock to reference (ltr) mode 1000 ppm dco frequency error for lol deassert with respect to nominal, data collected in ltr mode 250 ppm lol assert response time 2. 4576 gbps 51 s 9.8304 g bps 18 s acquisition time lock to data (ltd) mode 2. 4576 gbps 0.5 ms 9.8304 gbps 0.5 ms optional ltr mode 1 6.0 ms data rate readback accuracy coarse readback 5 % fine readback in addition to reference clock accuracy 100 p pm power supply voltage vcc 1.14 1.2 1.26 v vdd 2.97 3.3 3.63 v vcc1 1.62 1.8 3.63 v power supply current 0 db eq i nput mode , clock output dis abled vcc 2.4576 gbps 182.0 ma 3. 072 gbps 159.1 ma 4. 9152 gbps 180.8 ma 6.144 gbps 190.5 ma 9.8304 gbp s 217.3 ma vdd 2.4576 gbps 8.6 ma 3.072 gbps 9.0 ma 4.9152 gbps 8.8 ma 6.144 gbps 8.9 ma 9.8304 gbps 9.1 ma
ADN2905 data sheet rev. a | page 4 of 27 parameter test conditions/comments min typ max unit vcc1 2.4576 gbps 31.7 ma 3.072 gbps 16.2 ma 4.9152 gbps 31.8 ma 6.144 gbps 16.1 ma 9.83 04 gbps 32.8 ma total power dissipation 0 db eq i nput mode , clock output dis abled 2.4576 gbps 305.7 mw 3. 072 gbps 249.3 mw 4. 9152 gbps 304.5 mw 6.144 gbps 287.7 mw 9.8304 gbps 349.5 mw operating temperature range ?40 +85 c 1 this typica l acquisition specification applies to all selectable reference clo ck frequencies in the range of 11.05 mhz to 176.8 mhz . jitter specification s t a = t min to t max , vcc = vcc min to vcc max , vcc1 = vcc1 min to vcc1 max , vdd = vdd min to vdd max , vee = 0 v, i nput d ata p attern = prbs 2 23 ? 1 , ac - coupled to 100 ? differential termination load, i 2 c register default settings , unless other wise noted. table 2 . parameter symbol test conditions/comments min typ max unit t ransmitter j itters deterministic jitter t_dj cpri = 9.8304 gbps, k28.5 + d5.6 and k28.5 + d16.2 6.98 p s random jitter t_rj cpri = 9.8304 g bps, k28.5 + d5.6 and k28.5 + d16.2 0. 36 p s duty cycle distortion t_dcd cpri = 9.8304 gbps, k28.5 + d5.6 and k28.5 + d16.2 0.57 ps total jitter tj sff -8431, 64b/66b, 10.3125 gbps 13.6 ps data dependent jitter ddj sff - 8431, prbs 2 9 ? 1 , 10.3125 gbps 7.37 ps data dependent pulse width shrinkage ddpws sff - 8431, prbs 2 9 ? 1 , 10.3125 gbps 4.58 ps uncorrelated jitter uj sff -8431, 64b/66b, 10.3125 gbps 0.14 ps receiver jitters total jitter tolerance tj t sff - 8431, 10.3125 gbps 82.4 ps 99% jitter j2 sff - 8431, 10.3125 gbps 55.5 ps data dependent pulse width shrinkage ddpws sff - 8431, 10.3125 gbps 33.7 ps
data sheet ADN2905 rev. a | page 5 of 27 output and timing sp ecifications t a = t min to t max , vcc = vcc min to vcc max , vcc1 = vcc1 min to vcc1 max , vdd = vdd m in to vdd max , vee = 0 v, input data pattern = prbs 2 23 ? 1, ac - coupled to 100 ? differential termination load, i 2 c register default settings, unless otherwise noted. table 3 . parameter symbol test conditions/comments min typ max unit cml output characteristics data differentia l output swing 9.8304 g bps , data_swing[3:0] = 0xc (default) 535 600 672 mv p - p 9.8304 g bps , data_swing[3:0] = 0xf (maximum) 668 724 771 mv p - p 9.8304 g bps , data_swing[3:0] = 0x4 (minimum) 189 219 252 mv p - p output voltage high v oh dc - couple d vcc ? 0.05 vcc ? 0.025 vcc v low v ol dc - coupled vcc ? 0.36 vcc ? 0.325 vcc ? 0.29 v cml output timing characteristics rise time 20% to 80%, at 9.8304 g bps , datoutn/datoutp 17.4 32.6 46.5 p s 20% to 80%, at 9.8304 gbps , clkoutn/clkoutp 22.2 28.3 3 3.1 p s fall time 80% to 20%, at 9.8304 gbps , datoutn/datoutp 17.5 33 49.1 p s 80% to 20%, at 9.8304 gbps , clkoutn/clkoutp 23.9 29.2 33.7 p s setup time, full rate clock t s see figure 2 0.5 ui hold time, full rate clock t h see figure 2 0.5 ui setup time, ddr mode t s see figure 3 0.5 ui hold time, ddr mode t h see figure 3 0.5 ui i 2 c interface dc characteristics lvttl input voltage high v ih 2.0 v low v il 0.8 v input current v in = 0.1 vdd or v in = 0.9 vdd ? 10.0 +10.0 a output low voltage v ol i ol = 3.0 ma 0.4 v i 2 c interface timing see figure 14 sck clock frequency 400 khz sck pulse width high t high 600 n s sck pulse width low t low 1300 n s start condition hold time t hd;sta 600 ns start condition setup time t su;sta 600 ns data setup tim e t su;dat 100 ns data hold time t hd;dat 300 ns sck/sda rise/fall time 1 t r /t f 20 + 0.1 c b 300 ns stop condition setup time t su;sto 600 ns bus free time between stop and start conditions t buf 1300 ns lvttl dc input characterisitics (i 2 c_ad dr) input voltage high v ih 2.0 v low v il 0.8 v input current high i ih v in = 2.4 v 5 a low i il v in = 0.4 v ?5 a lvttl dc output characterisitics (los/lol) output voltage high v oh i oh = 2.0 ma 2.4 v low v ol i ol = ?2.0 ma 0.4 v
ADN2905 data sheet rev. a | page 6 of 27 parameter symbol test conditions/comments min typ max unit reference clock characteristics optional ltr mode input compliance voltage (single - ended) v cm no input offset, no input current, see figure 21, ac - coupled input 0.55 1.0 v minimum differential input drive see figure 21 , ac - coupled, differential input 100 mv p - p reference frequency 11.05 176.8 mhz required accuracy 2 ac - coupled, differential input 100 ppm 1 c b is the total capacitance of one bus line in picofarads (pf). if mixed with high speed (hs) mode devices, faster rise/fall times are allowed (refer to the philips i 2 c bus specification , version 2.1). 2 required accuracy in dc - coupled mode is guaranteed by design as long as the clock common - mode voltage output matches the reference clock common - mode voltage range. t iming diagrams int_clkp datoutp/ datoutn t s t h 12624-002 fig ure 2. data to clock timing (full rate clock mode) int_clkp datoutp/ datoutn t h t s 12624-003 figure 3. data to clock timing (half - rate clock/ddr mode) da t out p da t outn da t out p ? d a t outn 0v v se v se v diff 12624-004 figure 4. single - ended vs. differential output amplitude relations hip
data sheet ADN2905 rev. a | page 7 of 27 absolute maximum rat ings table 4 . parameter rating supply voltage (vcc = 1.2 v ) 1.26 v supply voltage (vdd and vcc1 = 3.3 v ) 3.63 v maximum input voltage ( refclkp / refclk n, nin/pin ) 1.26 v minimum input voltage ( refclkp / ref clk n, nin/pin) vee ? 0.4 v maximum input voltage ( sda, sck, i 2 c_ addr ) 3.63 v minimum input voltage (sda, sck, i 2 c_addr) vee ? 0.4 v maximum junction temperature 1 2 5c storage temperature range ? 65c to +150c lead temperature (soldering , 10 s ec ) 300c stresses at or ab ove those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specifica tion is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal characterist ics thermal resistance thermal resistance is specified for the worst - case conditions, that is, a device soldere d in a circuit board for surface - mount packages , for a 4 - layer board with the exposed paddle soldered to vee . table 5 . thermal resistance package type ja 1 jb 2 jc 3 unit 24- lead lfcsp 45 5 11 c/w 1 junction to ambient. 2 juncti on to base. 3 junction to case. esd caution
ADN2905 data sheet rev. a | page 8 of 27 pin configuration an d function descripti ons notes 1. nc = no connect. do not connect to this pin. 2. exposed pad on bottom of the package must be connected to vee electrically. vcc pin nin vee los lol vee vcc1 vdd nc nc vee datoutp nc vdd vcc datoutn vcc vcc refclkn refclkp sda sck i 2 c_addr 12624-005 2 1 3 4 5 6 18 17 16 15 14 13 8 9 10 1 1 7 12 20 19 21 22 23 24 ADN2905 t op view (not to scale) pin 1 indic a t or figure 5. pin configuration table 6 . pin function descriptions pin no. mnemonic type 1 description 1 vcc p 1.2 v supply for limiting amplifier. 2 pin a i positive differential data input (cml) . 3 nin a i negative differential data input (cml) . 4 vee p g round for limiting amplif ier . 5 los do loss of signal output ( active high ) . 6 lol do loss of lock output (active high). 7 vee p digital control oscillator ( dco ) ground . 8 vcc1 p 1.8 v to 3.3 v dco supply . 9 vdd p 3.3 v high supply . 10 nc n/a no connect. do not connect to this pin. leave this pin floating 11 nc n/a no connect. do not connect to this pin. leave this pin floating 12 vee p ground for cml output drivers . 13 vcc p 1.2 v supply for cml output driver s . 14 datoutn do negative differential re t imed data output (cml) . 15 dat outp do positive differential re t imed data output (cml) . 16 nc di no co nnect. tie this pin to vee ( g round ) . 17 vdd p 3.3 v high supply . 18 vcc p 1.2 v core digital supply . 19 sck di clock for i 2 c . 20 sda d io bidirectional data for i 2 c . 21 vcc p 1.2 v core supply . 22 i 2 c_addr di i 2 c address setting. sets the device i 2 c a ddress to 0x80 when i 2 c_addr = 0 . sets the device i 2 c address to 0x82 when i 2 c_addr = 1 . 23 refclkn di negative reference clock input ( optional ) . 24 refclkp di positive reference clock input ( optional ) . n/a epad p exposed pad (vee) . the exposed pad on the bottom of the device package must be connected to vee electrically. the exposed pad w ork s as a heat sink. 1 p is power, ai i s analog input, di is digital input, do is digital output, dio is digital input/output, and n/a is not applicable.
data sheet ADN2905 rev. a | page 9 of 27 t ypical performance c haracteristics t a = 25c , vcc = 1.2 v , vcc1 = 1.8 v, vdd = 3.3 v , vee = 0 v, i nput d ata p attern = prbs 2 15 ? 1, ac - couple d inputs and outputs , unless otherwise noted. 12624-006 figure 6. output eye diagram at cpri 16 = 9.8304 gbps , t ime = 16.95 ps/div , a mplitude = 116 mv /div 12624-007 figure 7. output eye diagram at cpri 12 = 6.144 gbps , t ime = 27.13 ps/div , a mplitude = 118 mv /div 0 ?40 ?15 ?5 ?20 ?25 ?30 ?35 ?10 1m 10m 100m 1g 10g 100g log magnitude (db) frequency (hz) 12624-008 figure 8. typical s11 spectrum performance 0.6 0.5 0.4 0.3 0.2 0.1 0 0 16 14 12 10 8 6 4 2 ber eq setting typical adaptive eq setting 12624-009 figure 9 . ber in equalizer mode vs. eq compensation at cpri 16 = 9.8304 gbps ( with a signal of 400 mv p - p d iff erential , on 15 in ch fr4 traces, with variant eq compensation, including adaptive eq)
ADN2905 data sheet rev. a | page 10 of 27 i 2 c interface timing a nd internal register description s 1 sla ve address[6:0] set b y pin 22 msb = 1 0 = w 1 = r r/w ctr l 0 0 0 0 0 x x 12624-010 figure 10 . slave address configuration s s = start bit p = stop bit a(s) = acknowledge by slave a(m) = acknowledge by master a(m) = no acknowledge by master s slave addr, lsb = 0 (w) slave addr, lsb = 1 (r) a(s) a(s) subaddr a(s) data a(m) data p a(m) 12624-012 figure 11 . i 2 c read data transfer s sla ve addr, lsb = 0 (w) a(s) a(s) a(s) dat a subaddr a(s) p dat a 12624-0 1 1 figure 12 . i 2 c write data transfer st art bit s st op bit p ack ack wr ack d0 d7 a0 a7 a5 a6 sla ve addr[4:0] sla ve address subaddress dat a subaddr[6:1] dat a[6:1] sck sda 12624-013 figure 13 . i 2 c data transfer timing t buf sda s s p s sck t f t low t r t f t hd;s t a t hd;d a t t su;d a t t high t su;s t a t su;s t o t hd;s t a t r 12624-014 figure 14 . i 2 c interface timing diagram
data sheet ADN2905 rev. a | page 11 of 27 register map writing to registe r bits o ther than those clearly labeled is not recommended and may cause unintended results. table 7 . internal register map 1, 2 reg . name r/w addr . (hex) default (hex) d7 d6 d5 d4 d3 d2 d1 d0 readback/status freqmeas0 r 0x0 n/a freq0[7:0] (rate_freq[7:0]) freqmeas1 r 0x1 n/a freq1[7:0] (rate_freq[15:8]) freqmeas2 r 0x2 n/a freq2[7:0] (rate_freq[23:16]) freq_rb1 r 0x4 n/a vcosel[7:0] freq_rb2 r 0x5 n/a x fullrate divrate[3:0] vcosel[9:8] statusa r 0x6 n/a x x r eserved lol s t atus r eserved static lol x rate_meas_ comp general control ctrla r/w 0x8 0x10 0 cdr_ mode [2:0] 0 reset s tatic lol rate_ meas_en rate_meas_ reset ctrlb r/w 0x9 0x0 8 software_ reset init_ freq _acq cdr b ypass lol c onfig 1 r eserved 0 0 ctrlc r/w 0xa 0x05 0 0 0 0 0 refclk_ pdn 0 1 fll control ltr_mode r/w 0xf 0x00 0 lol d ata fref_range [1:0] data_to_ref_ratio [3:0] dpll control dplla r/w 0x10 0x1c 0 0 0 edge_sel [1:0] tranbw [2:0] dplld r/w 0x13 0x0 2 0 0 0 0 0 r eserved to 0 dll_slew [1:0] phase r/w 0x14 0x00 0 0 0 0 sample_phase [3:0] la_eq r/w 0x16 0x 08 rx_ term_ float input_sel [1:0] adaptive_ eq_en eq_boost [3:0] output control outputa r/w 0x1e 0x0 0 0 0 data s quelch datout_ disable 1 ddr_ disable data_ polarity reserved outputb r/ w 0x1f 0xcc data_swing [3:0] r eserved prbs control prbs gen 1 r/w 0x39 0x00 0 0 data_ cid_bit data_ cid_en 0 data_ gen_ en data_gen_mode [1:0] prbs gen 2 r/w 0x3a 0x00 data_cid_length [7:0] prbs gen 3 r/w 0x3b 0x00 prog_data [7:0] prbs gen 4 r/w 0x3c 0x00 prog_data [15:8] prbs gen 5 r/w 0x3d 0x00 prog_data [23:16] prbs gen 6 r/w 0x3e 0x00 prog_data [31:24] prbs rec 1 r/w 0x3f 0x00 0 0 0 0 data_ receiver_ clear data_ receiver_ enable data_receiver_ mode [1:0] prbs rec 2 r 0x40 0x00 prbs_error_count[7:0] prb s rec 3 r 0x41 0x00 prbs_error prbs rec 4 r 0x42 n/a data_loaded [7:0] prbs rec 5 r 0x43 n/a data_loaded [15:8] prbs rec 6 r 0x44 n/a data_loaded [23:16] prbs rec 7 r 0x45 n/a data_loaded [31:24]
ADN2905 data sheet rev. a | page 12 of 27 reg . name r/w addr . (hex) default (hex) d7 d6 d5 d4 d3 d2 d1 d0 id/revision rev r 0x48 0x54 rev[7:0] id r 0x49 0 x15 id[7:0] hi_code r 0x20 0xad reserved lo_code r 0x21 0x63 reserved 1 x means dont care. 2 n/a means not applicable. table 8 . status register, status a ( address 0x6) bit ( s ) bit name bit description d5 r eserved x d4 lol s tatus 0 = locked 1 = frequency acquisition mode d3 r eserved x d2 static lol 0 = no lol event since last reset 1 = lol event sinc e last reset; clear using the reset static lol bit d0 rate_meas_comp rate measurement complete 0 = frequency measurement incomplete 1 = frequency measurement comple te; clear using the rate_meas_reset bit table 9 . control register, ctrla ( address 0x8) bit(s) bit name bit description d7 reserved reserved to 0. [ d 6 : d 4 ] cdr_ mode [2:0] cdr m odes . 000 = lock to data (ltd). 010 = lock to refe rence (ltr). 001, 011 = r eserved. d3 reserved reserved to 0. d2 reset static lol in factory defau lt mode, this bit is set to 0. in the static lol mode , write 1 and then write 0 to clear s tatic lol bit (d2 of the status r egister) . d1 rate_meas_en fine data r ate measurement enable. set to 1 to initiate a rate measurement. d0 rate_meas_reset rate measurement reset. set to 1 to clear a rate measurement. table 10. control register, ctrlb ( address 0x9) bit(s) bit name bit descripti on d7 software_reset software r eset. write a 1 followed by a 0 to reset the device . d6 init_freq_acq initiate frequency acquisition. write a 1 followed by a 0 to initiate a frequency acquisition (optional). d5 cdr bypass cdr bypass. 0 = cdr enabled. 1 = cdr bypassed. d4 lol c onfig lol configuration. 0 = normal lol. 1 = static lol. d3 reserved reserved to 1. d2 reserved reserved to 0. [ d1:d0 ] reserved reserved to 0.
data sheet ADN2905 rev. a | page 13 of 27 table 11. control register, ctrlc ( address 0xa) bit ( s ) bit name bit description [d7:d3] reserved reserved to 0. d2 refclk_pdn r eference clock p ower - d own . write a 0 to enable the reference clock . d1 reserved reserved to 0. d0 reserved reserved to 1. table 12 . lock t o refer ence clock mode programming register , ltr_mode 1 ( address 0xf) bit ( s ) bit name bit description d7 reserved reserved to 0 d6 lol data lol data 0 = clk vs. reference clock during tracking 1 = clk vs. data during tracking [ d5 : d4 ] fref_range [1:0] f ref range 00 = 11.05 mhz to 22.1 mhz 01 = 22.1 mhz to 44.2 mhz 10 = 44.2 mhz to 88.4 mhz 11 = 88.4 mhz t o 176.8 mhz [ d3 : d0 ] data_to_ref_ratio [3:0] data to reference ratio 0000 = ? 0001 = 1 0010 = 2 n = 2 (n ? 1) 1010 = 512 1 where div _ f ref is the divided down reference referred to the 11.05 mhz t o 22.1 m hz band (see the reference clock (optional) section). data rate /2 ( ltr_mode[3:0] ? 1) = refclk /2 ltr_mode[5:4] table 13. d pll control register, dplla ( address 0x10) bit ( s ) bit name bit description [ d7 : d5 ] reserved reserved to 0. [ d4 : d3 [ edge_sel [1:0] edge for phase detection. see the edge se lect section for further details. 00 = rising and falling edge data . 01 = rising edge data . 10 = falling edge data . 11 = rising and falling edge data . [ d2 : d0 ] tranbw [2:0] transfer b andwidth . scales transfer bandwidth. default value is 4, resu lting in the cpri 16: 9.8304 gbps default bw shown in table 2 . see the transfer bandwidth section for further details. transfer bw = default transfer bw ( tranbw [2:0] /4) table 14. d pll control register, dplld ( address 0x13) bit ( s ) bit name bit description [ d7 : d 2 ] reserved reserved to 0. [ d1 : d0 ] dll_slew[1:0] dll slew. sets the bw of the dll. see the dll slew section for further details. table 15 . phase control register, phase ( address 0x14) bit ( s ) bit name bit description [ d7 : d4 ] reserved reserved to 0. [ d3 : d0 ] sample_phase[3:0] adjust a the phase of the sampling instant for data rates above 5.65 gbps in steps of 1/32 ui. this register is in twos complement notation. see the sample phase adjust section for further details.
ADN2905 data sheet rev. a | page 14 of 27 table 16. input stage programming register , la_eq ( address 0x16) bit ( s ) bit name bit description d7 rx_term_float r eceiver (rx) termination float . 0 = termination common - mode driven . 1 = termination common - mode floated . [ d6 :d 5 ] input_sel[1:0] input stage select . 01 = equalizer . 10 = 0 db eq mode . 00, 11 = undefined . d4 adaptive_eq_en en able adaptive eq . 0 = manual eq control . 1 = adaptive eq enabled . [ d3 : d0 ] eq_boost[3:0] equalizer gain. these bits set the eq gain. see the passive equalizer section for further details. table 17. o utput control register , outputa ( address 0x1e) bit ( s ) bit name bit description [ d7 : d6 ] reserved reserved to 0 d5 data squelch squelch 0 = normal data 1 = squelch data d4 datout_disable data output disable 0 = data output enabled 1 = data out put disabled d3 reserved reserved to 1 d2 ddr_disable double data rate 0 = ddr clock enabled 1 = ddr clock disabled d1 data_polarity d ata polarity 0 = normal data polarity 1 = flip data polarity d0 reserved reserved to 0 table 18 . output swing register, outputb ( address 0x1f) bit ( s ) bit name bit description [ d7 : d4 ] data_swing[3:0] adjust data outpu t amplitude. step size is approximately 50 mv differential . default register value is 0xch . ty pical differential data ou tput amplitudes are 0x1 to 0x3 = invalid. 0x4 = 200 mv. 0x5 = 250 mv. 0x6 = 300 mv. 0x7 = 345 mv. 0x8 = 390 mv. 0x9 = 440 mv. 0xa = 485 mv. 0xb = 530 mv. 0xc = 575 mv. 0xd = 610 mv. 0xe = 640 mv. 0xf = 655 mv. [ d3 : d0 ] r eserved default = 0xch .
data sheet ADN2905 rev. a | page 15 of 27 theory of operation the ADN2905 implements a data recovery for cpri data rates from 614.4 mbps to 9 .8304 gbps . the front end is configurable to either equalize or 0 db eq the nonreturn - to - zero ( nrz ) input waveform to full - scale digital logic levels , or to pass a full digital logic signal . the user can choose from two input stages to process the data: a high - pass passive equalizer with up to 10 db of boost at 5 ghz , or 0 db eq mode with approximately 250 mv p - p sensitivity at cpri rate 9.8304 gbps . when the input signal is corrupted due to fr - 4 or other impairments in the printed circuit board ( pcb ) tra ces, a passive equalizer can be one of the signal integrity options. the equalizer h igh frequency boost is configurable through the i 2 c registers , in place of the factory default setting s . a user enabled adaptation is included that automatically adjusts th e equalizer to achieve the widest eye opening. the equalizer can be manually set for any data rate, but adaptation is available only at data rates greater than 5.5 gb p s. when a signal is present ed to the data recovery , t he ADN2905 act s as a delay - locked and phase - locked loop (pll) circuit for clock recovery and data retiming from an nrz encoded data stream. input data is sampled by a high speed clock. a digital down sampler accommodates data rates spanning three orders of magnitude. downsampled data is applied to a binary phase detector. the phase of the input data signal is tracked by two separate feed - back loops. a high speed , delay - locked loop (dll) path cascades a digital integrator with a digitally controlled phase shifter on the d igital c ontrol o scillator ( dco ) clock to track the high frequency components of jitter. a separate phase control loop , comp osed of a digital integrator and dco , tracks the low frequency components of jitter. the initial frequency of the dco is set by a third loop that compares t he dco frequency with the input data frequency. this third loop also sets the decim ation ratio of the digital down sampler. the de lay - locked and phase - locked loops together track the phase of the input data. for example, when the clock lags the input data, the phase detector drives the dco to a higher frequency and decreases the delay of the clock through the phase shifter ; both of t hese actions reduce the phase error between the clock and data. because the loop filter is an integrator, the static phase error is driven to zero. another view of the circuit is that the phase shifter implements the zero required for frequency compensati on of a second - order phase - locked loop, and this zero is placed in the feedback path and , therefore , does not appear in the closed - loop transfer function. because this circuit has no zero in the closed - loop transfer, jitter peaking is eliminated . the dela y - locked and phase - locked loops simultane ously provide wideband jitter accommodation and narrow - band jitter filtering. the simplified block diagram in figure 15 shows that z(s)/x(s) is a second - order , low - pass jitt er transfer function that provid es excellent filtering. the low frequency pole is formed by dividing the gain of the pll by the gain of the dll, where the upsampling and zero - order hold in the dll has a gain approaching n at the transfer bandwidth of the l oop. note that the jitter transfer has no zero, unlike an ordinary , second - order phase - locked loop , which means that the main pll has no jitter peaking. this no jitter peaking featur e makes the circuit ideal for signal regenerator applications where jitter peaking in a cascade of regenerators can contribute to hazardous jitter accumulation. the error transfer, e(s)/x(s) , has the same high - pass form as an ordinary phase - locked loop up to the slew rate limit of the dll with a binary phase detector. this tran sfer function is free to be o ptimized to give excellent wide band jitter accommodation because the jitter transfer function, z(s)/x(s), provides the narrow - band jitter filtering. psh z(s) recovered clock k dl l i ? z ?1 k dco s i ? z ?n i ? z ?1 k pll tranbw i ? z ?1 n n del a y -locked loo p (dll) phase-locked loo p (pll) zero-order hold sample clock input dat a n bina r y phase detec t or x(s) = k pll tranbw ? k dco s n psh k dll + k pll tranbw k dco z(s) x(s) 12624-015 figure 15 . cdr jitter block diagram
ADN2905 data sheet rev. a | page 16 of 27 the dela y - locked and phase - locked loops contribute to overall jitter accommodation . at low frequencies of input jitter on the data signal, the integrator in the loop filter provides high gain to track large jitter amplitudes with small phase error. in this case, t he oscillator is frequency modulated , and jitter is tracked as in an ordinary phase - locked loop. the amount of low frequency jitter that can be tracked is a function of the dco tuning range. a wider tuning range provides more accommodation of low fre quency jitter. the internal loop control word remains small for small jitter frequency, so that the phase shifter remains close to the center of its range and, th erefore , contributes little to the low frequency jitter accommodation . at medium jitter frequencies , the gain and tuning range of the dco are not large enough to track input jitter. in this case, the dco control word becomes large and saturates. as a result, the dco frequency remains at an extreme of its tuning range. the size of the dco tuning range, t herefore, has only a small effect on the jitter accommodation . the delay - locked loop control range is larger ; therefore , the phase shifter track s the input jitter. an infinite range phase shifter is used on the clock. consequently, the minimum range of timi ng mismatch between the clock at the data sampler and the retiming clock at the output is limited by the depth of the fifo to 32 ui . there are two ways to acqu ire the data rate. the default mode is for the frequency to lock to the input data, where a fini te state machine extracts frequency measurements from the data to program the dco and loop division ratio so that the sampling frequency matches the data rate to within 250 ppm . the pll is enabled, driving this frequency difference to 0 ppm . the second mod e is to lock to reference (ltr) , in which case the user provides a reference clock between 11.05 mhz and 176.8 mhz. division ratios must be written to a serial port register.
data sheet ADN2905 rev. a | page 17 of 27 functional descripti on frequency acquisitio n the ADN2905 acquires its frequency from the data over a range of data frequencies from 614.4 m bps to 9.8304 g bps . the lock detector circuit compares the frequen cy of the dco and the frequency of the incoming data. when these frequencies differ by more than 1000 ppm, the lol pin is asserted , and a new fre - quency acquisition cycle is initiated. the dco frequency is reset to the lowest point of its range, and the in ternal division rate is set to its lowest value of n = 1 , which is the highest octave of data rates. the frequency detector then compares this sampling rate frequency to the data rate frequency and either increases n by a factor of 2 if the sampling rate f requency is greater than the data rate frequency, or increases the dco frequency if the data rate frequency is greater than the data sampling rate frequency . initially, the dco frequency is incremented in large steps to aid fast acquisition. as the dco fre quency approaches the data frequency, the step size is reduced until the dco frequency is within 250 ppm of the data freq uency, at which point lol is de asserted. when lol is de asserted, the frequency - locked loop is turned off. the pll or dll pulls in the d co frequency until the dco frequency equals the data frequency. e dge s elect a binary , or alexander , phase detector drives both the dll and pll at all division rates. duty cycle distortion on the received data leads to a dead band in the phase detector tran sfer function if phase errors are measured on both rising and falling data transitions. this dead band leads to jitter generation of unknown spectral composition with potentially large peak - to - peak amplitudee. the recommended usage of the device when the d c offset loop is disabled is to compute phase errors exclusively on either the rising data edges with edge_sel[1:0] (bits[d4:d3] in register 0x10) = 1 (decimal) or on the falling data edges with edge_sel[1:0] = 2 . the alignment of the clock to the rising d ata edges with edge_ sel [1:0] = 1 is represented by the top two curves in figure 16. duty cycle distortion with n arrow 1s moves the significant sampling instance where data is sampled to the right of center. the alignment of the c lock to the falling data edges with edge_ sel [1:0] = 2 is represented by the first and third curves in figure 16. the significant sampling instance moves to the left of center. sample phase adjust ment for rates above 5. 6 5 gbps can be used to move the significant sampling instance to the center of the n arrow 1 (or n arrow 0) for best jitter tolerance. edge_sel[1:0] edge_sel = 2 clk1 clk2 data 12624-016 figure 16 . phase detector timing dll slew jitter tolerance beyond the transfer bandwidth of the cdr is det ermined by the slew rate of the delay - locked loop implement - ing a delta modulator on phase. setting dll_slew [1:0] = 2 , ( the default value ) in the register 0x13 configures the dll to track 0.75 ui p - p jitter at the highest frequency breakpoint at 4 mhz for cpri = 9.8304 gbps . dplld[1:0] can be set to 0, giving lower jitter generation on the recovered clock and better high frequency jitter tolerance. sample phase adjust ment the phase of the sampling instant can be adjusted using the i 2 c interface when the dev ice operat es at data rates of 5.65 gbps or higher by writing to sample_phase [3:0] ( bits [ d 3: d0] in register 0x14 ) . this feature allows the user to adjust the sampling instant to improv e the ber and j itter t olerance. although the default sampling instant cho sen by the cdr is sufficient in most applications, when dealing with some degrade d input signals , the ber and jitter tolerance performance can be improved by manually adjusting the phase. a total adjustment ra nge of 0.5 ui is available , with 0.25 ui in ea ch direction, in increments of 1/32 ui. sample_phase [3:0] is a twos complement number . t he relationship between data and the sampling clock is shown in figure 17. transfer bandwidth the transfer bandwidth can be adjusted using th e i 2 c interface by writing to the tranbw [2:0] bits in register 0x10. the default value is 4. when set to values below 4, the transfer bandwidth is reduced . w hen set to values above 4, the transfer bandwidth is increased. the resulting transfer bandwidth (bw ) is based on the following formula: ? ? ? ? ? ? = 4 ] tranbw[2:0 ansfer bw default tr w transfer b for example, at cpri 16 ( 9.8304 gbps ) , the default transfer bandwidth is approximately 2 mhz. the resulting transfer bandwidth when tranbw[2:0] is changed is ? tranbw[2:0] = 1: transfer bw = 500 k hz ? tranbw[2:0] = 2: transfer bw = 1.0 mhz ? tranbw[2:0] = 3: transfer bw = 1.5 mhz ? tranbw[2:0] = 4: transfer bw = 2.0 mhz (default) ? tranbw[2:0] = 5: transfer bw = 2.5 mhz ? tranbw[2:0] = 6: transfer bw = 3.0 mhz ? tranbw[2:0] = 7: transfer bw = 3.5 mhz reducing the transfer band width is commonly used in optical trans port network (otn ) applications. never set tranbw[2:0] to 0, because thi s makes the cdr open loop. also note that setting tranbw[2:0] above 4 can cause a slight increase in jitter generation and poten tial jitter peaking.
ADN2905 data sheet rev. a | page 18 of 27 data clock phase = 4 phase = 7 phase = ?4 phase = ?8 phase = 0 (default) 12624-017 figure 17 . data vs. sampling clock p assive e qualizer a passive equalizer is available at the input to equalize large signals that have undergone distortion due to pcb traces, vias, or connectors. the adap tive eq functions only at data rates greater than 5.5 gb p s . therefore, at rates less than 5.5 gb p s, the eq must be manually set. the equalizer can be manually set using the la_eq register ( register 0x16) . an adaptive loop is also available t o optimize the eq setting based on characteristics of the rec ei ved eye at the phase detector. if the chann el is known in advance, set the eq manually to obtain the best performance; however, the adaptive eq find s the best setting in most cases. table 19 lists the typical eq setting s for several trace lengths. the values in table 19 are based on measurements taken on a test board with simple fr - 4 trace s. table 20 lists the typica l maximum reach in inches of fr - 4 of the eq at several data rates. if a real channel includes lossy connectors or vias, the fr - 4 reach length is lower. for any real - world system, it is highly recommended to test several eq settings with the real channel to ensure the best signal integrity. table 19. eq settings vs. trace length on fr -4 trace length ( i nches) typ ical eq setting 6 10 10 12 15 14 20 to 30 15 table 20. typical eq reach on fr - 4 vs. maximum data rates supported maximum data rate (gbps) typical eq reach on fr - 4 ( i nches) 4 30 8 20 10 15 11 10 0 d b eq the 0 db eq path connects the input signal directly to the digital logic inside the ADN2905 . the 0 db eq is useful at lower data rates where the signal is large (therefore, the limiting amplifier is not needed, and power can be saved by deselecting the limiting amplif ier) and unimpaired (therefore, the equalizer is not needed). the signal swing of the internal digital circuit is 600 mv p - p diff erential , th e minimum signal a mplitude that must be provided in 0 db eq mode . in 0 db eq mode , the internal 50 ? termination re sistors can be configured in one of two ways, either floated or tied to v cc = 1.2 v (see figure 22 an d table 23 ) . by setting the rx _term_float bit ( bit d7 in register 0 x 16) to 1, these 50 ? termination resistors are floated internal to the ADN2905 (see figure 25 ). by sett ing the rx_term_float bit to 0 , these 50 ? termi nation resistors are connected to v cc = 1.2 v (see figure 26 ). in both termination cases, the user must ensure a valid com mon - mode voltage on the input. w he n the termina tion is floated, the two 50 ? resistors are a purely differential termination. the input must conform to the range of signals shown in figure 28. when the termination is connected to a 1.2 v v cc power supply (see figure 26 and figure 27 ), the common - mode voltage is created by the driver circuit and the 50 ? resistors on the ADN2905 . for example, the driver can be an open - drain switched current (see figure 26) , and the 50 ? resistors return this current to v cc . in figure 26, t he common - mode voltage is created by both the current and the resistors. in this case, ensure that the current is a minimum of 6 ma , which gives a single - ended swing of 300 mv or a differential swing of 600 mv p - p differential, with v cm = 1.05 v (see figure 28) . the maximum current is 10 ma , which gives a single - end ed 500 mv swing and a differential 1.0 v p - p swing with v cm = 0.95 v ( see figure 29). another possibility is to back terminate the switched cu rrent driver , as shown in figure 27, with the two v cc supplies having the same potential. in this example , the current is returned to v cc by t he t wo 50 ? resistors in parallel, or 25 ?, so that the minimum current is 12 ma and the maximum current is 20 ma. lock detector operat ion the lock detector on the ADN2905 has three modes of operation: normal mode, ltr mode, and static lol mode.
data sheet ADN2905 rev. a | page 19 of 27 normal mode in normal mode, the ADN2905 is a multiple rate data recovery device t hat locks onto the cp ri data rate from 614.4 m bps to 9.8304 g bp s without the use of a reference clock as an acquisition aid. in this mode, the lock detector monitors the frequency difference between the dco and the input data frequency, and deasserts the loss of lock signal, w hich appears on lol (pin 6) when the dco is within 250 ppm of the data frequency. this enables the digital pll ( dpll ) , which pulls the dco frequency in the remaining amount and acquires phase lock. when locked, if the input frequency error exceeds 1000 ppm (0.1%) , the loss of lock signal is re asserted and control returns to the frequency loop, which begins a new frequency acquisition. the lol pin remains asserted until the dco locks onto a valid input data stream to within 250 ppm frequency error. this hyst eresis is shown in figure 18. lol 0 ?250 250 1000 f dco error (ppm) ?1000 1 12624-018 figure 18 . transfer function of lol lol detector operation using a reference clock (ltr mode) in l ock to reference (ltr) mode , a reference clock is used as an acquisition ai d to lock the ADN2905 dco . ltr mode is enabled by setting the cdr_ mode [2:0] bits to 2 ( bits[d6:d4] in register 0x8) . the user must also write to the fref_range [1:0] bits and the data_to_ ref_ratio [3:0] bits ( bits[d5:d4] and bits[d 3 :d0] in register 0xf) to set the reference frequency range and the divide ratio of the data rate with respect to the reference frequency. finally, the refe rence clock power down to the re ference clock buffer must be de asserted by writing a 0 to the refclk_pdn bit ( bit d2 in register 0xa) . to maintain fastest acquisition , keep bit d 0 in register 0xa set to 1. for more details, see the reference clock (optional) section. in ltr mode, the lock detector monitors the difference in fre - quency between the divided down dco and the divided down reference clock. the loss of lock signal, which appears on lol ( pin 6 ) , is deasserted when the dco is within 250 ppm of the desired frequency. this enables the dpll , which pulls in the dco frequency by the remaining amount with respect to the input data and acquires phase lock. when locked, if the frequency error exceeds 1000 ppm (0.1%) , the loss of loc k signal is re asserted and control returns to the frequency loop, which reacquires lock with respect to the reference clock. the lol pin remains asserted until the dco frequency is within 250 ppm of the desired frequency. this hysteresis is shown in figure 18. static lol mode the ADN2905 implements a static lol feature that indicates whether a loss of lock c ondition has ever occurred and remains asserted, even if the ADN2905 regains lock, until the static lol bit ( bit d2 in register 0x 6 ) is manually reset. if a loss of lock condition occurs , this bit is internally asserted to logic high. the static lol bit remains high even after the ADN2905 reacquire s lock to a new data rate. this bit can be reset by writing a 1 , followed by 0 , to the reset static lol bit ( bit d2 in register 0x8 ) . when reset, the static lol bit remains de asserted until another loss of lock condit ion occurs. writing a 1 to the lol configuration bit ( bit d 4 in register 0x9 ) causes the lol pin ( pin 6 ) to become a static lol indicator. in this mode, the lol pin mirrors the contents of the static lol bit ( bit d 2 in register 0x6 ) and has the functionali ty described previous ly . the lol configuration bit defaults to 0. in this mode, the lol pin operates in the normal operat ing mode; that is, it is asserted only when the ADN2905 is in acquisition mode and de asserts when the ADN2905 has reacquired lock. harmoni c detector the ADN2905 provides a harmonic detector that detects whether the input data has changed to a lower harmonic of the da ta rate than the one that the sampling clock is currently locked onto. for example, if the input data instantaneously changes from a cpri 16 ( 9. 8304 g bps ) to a cpri 4 ( 2.4 576 g bps ) bit stream, this can be perceived as a va lid cpri 16 bit stream becau se the cpri 4 data pattern is exactly 4 slower than the cpri 16 pattern. therefore , if the change in data rate is instantaneous, a 101 pattern at cpri 4 ( 2.4576 gbps ) is perceived by the ADN2905 as a 111100001111 pattern at cpri 16 ( 9.8304 gbps ) . if the change to a lower harmonic is instantaneous, a typical inferior cdr may remain locked at the higher data rate. the ADN2905 implements a harmonic detector that automati - cally identifies whether the input data has switched to a lower harmonic of the data rate than the one that the dco is currently locked onto. when a harmonic is identified, the lol pin is asserted , and a new frequency acquisition is initiated. the ADN2905 automati cally locks onto the new d ata rate, and the lol pin is de asserted. the time to detect a lock to harmonic is 2 16 ( t d /) where: 1/ t d is the new data rate. for example, if the data rate is switched from cpri 16 ( 9.8304 gbps ) to cpri 4 ( 2.4576 gbps ) , t d = 1/ 2.4 576 g hz. is the data transition density. most coding schemes seek to ensure that = 0.5, for example, prbs and 8b/10b. when the ADN2905 is placed in lock to reference mode, the harmonic detector is disabled. o utput disable and squelch th e ADN2905 offers output disable/squelch. the datoutp/ datoutn outputs can be disabled by setting the datout_ disable bit ( bit d 4 i n register 0x1e ) high . when an output is
ADN2905 data sheet rev. a | page 20 of 27 disabled, it is fully powered down, saving approximately 30 mw total power. t o set the data output while leaving the clock on, t he output data can be squelched by setting the data squelch bit ( bit d 5 in register 0x 1e ) high. in this mode , the data driver remains powered, but the data itself is forced to be a value of 0 or 1, depending on the setting of the data_polarity bit ( bit d 1 in register 0x1e). i 2 c interface the ADN2905 supports a 2 - wire, i 2 c - compatible, serial bus driving multiple peripherals. two inputs, serial data (sda) and serial clock (sck), carry information between any devices co n - nected to the bus. each slave device is recognized by a unique address. the slave address consists of the seven ms bs of an 8 - bit word. the upper six bits ( bits [6:1]) of the 7 - bit slave add ress are factory programmed to 100000. the lsb of the slave addres s ( bit 0) i s set by pin 22, i 2 c_addr . the lsb of the word specifies either a read or write operation (see figure 10). logic 1 corresponds to a read operation, whereas logic 0 corresponds to a write operation. to control the device on the bus, the following protocol must be used : 1. t he master initiates a data transfer by establishing a start condition, defined as a high to low transition on sda while sck remains high. this indicates that an address/data stream follows. 2. all periphera ls respond to the start condition and shift the next eight bits (the 7 - bit address and the r/w bit). the bits are transferred from msb to lsb. 3. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth cl ock pulse. this is an acknowledge bit. 4. all other devices withdraw from the bus at this point and maintain an idle condition. in t he idle condition , the device monitors the sda and sck lines waiting for the start condition and the correct transmitted addre ss. the r/w bit determines the direction of the data. logic 0 on the lsb of the first byte means that the master writes information to the peripheral. logic 1 on the lsb of the first byte means that the master reads information from the peripheral. the ADN2905 acts as a standard slave device on the b us. the data on the sda pin is eight bits long , supporting the 7 - bit addresses plu s the r/w bit. the ADN2905 has subaddresses to enable the user - accessible internal registers (see table 7 ) . the ADN2905 , therefore, interprets the first byte as the device address and the second byte as the starting subaddress. auto - in crement mode is supported, allowing data to be read from or written to the starting subaddress and each subsequent address without manually addressing the subsequent subaddress. a data transfer is always terminated by a stop condition. the user can also ac cess any unique subaddress register on a one - by - one basis without updating all registers. stop and start conditions can be detected at any stage of the data transfer. if these conditions are asserted out of sequence with normal read and write operations, t hey cause an immediate jump to the idle condition. during a given sck high period, issue one start condition, one stop condition, or a single stop condition followed by a single start condition. if the user issues an invalid subaddress, the ADN2905 does not issue an acknowledge and returns to the idle condition. if the user exceeds the highest subaddress while reading back in auto - in crement mode, the highest subaddress register contents continue to be output until the master device issues a no acknowledge. this indicates the end of a read. in a no acknowledge condition, the sda line is not pulled low on the ninth pulse. see figure 11 and figure 12 for sample read and write data transfers , respectively, and figure 13 for a more detailed timing diagram. reference clock (opt ional) a reference clock is not requir ed to perform data recovery with the ADN2905 . however, support for an optional reference clock is provided. the reference clock ca n be driven differentially or single - ended. if the reference clock is not used, float both the refclkp and refclkn pins . two 50 ? series resistors present a differential load between refclkp and refclkn. common mode is internally set to 0.56 vcc by a resist or divider between vcc and vee. see figure 19, figure 20 , and figure 21 for sample configurations. the reference clock input buffer accepts any differential signal with a peak - to - peak differential amplitude of greater than 100 m v. the p hase noise and duty cycle of the reference clock are not critical , and a 100 ppm accuracy is sufficient. 50? 50? vcc/2 refclk p refclkn ADN2905 buffer 24 23 12624-019 clock figure 19 . dc - coupled , differential refclk x configuration 50? 50? vcc/2 vcc refclk p out refclkn ADN2905 buffer 24 23 clk osc 12624-020 figure 20 . ac - coupled , single - ended refclk x configuration
data sheet ADN2905 rev. a | page 21 of 27 50? 50? vcc/2 refclkp refclkn ADN2905 buffer 24 23 refclk 12624-021 figure 21 . ac - coupl ed, differential refclk x configuration the reference clock can be used either as an acquisition aid for the ADN2905 to lock onto data, or to measure the frequency of the incoming data to within 0.01%. the modes are mutually exclusive because, in the first use, the user can force the device to lock onto only a known data rate ; in the second use, the user can measure an unknown data r ate . lock to refere nce mode is enabled by writing a 2 to the cdr_ mode [2:0] bits ( bits[d 6: d 4] in register 0x8 ) . an on - chip clock buffer must be powered on by writing a 0 to the refclk_ pd n bit ( bit d 2 in register 0xa ) . fine data rate read back mode is enabl ed by writing a 1 to the rate_meas_en bit ( bit d 1 in register 0x8 ) . e nabling lock to reference and data rate readback at the same time causes an indeterminate state and is not supported. using the reference clock to lock onto data in ltr mode, the ADN2905 locks onto a frequency derived from the reference clock according to the following equation: data rate /2 ( ltr_mode[3:0] ? 1) = refc lk /2 ltr_mode[5:4] the user must know exactly what the data rate is and provide a reference clock that is a function of this rate. the ADN2905 can still be used as a continuous rate device in this configuration if the user can provide a reference clock that has a variable frequency (see the an - 632 application note ). the re ference clock can have a frequency from 11.05 mhz to 176.8 mhz. by default, the ADN2905 expects a reference clock of between 11.05 mhz and 22.1 mhz. if the reference clock is between 22.1 mhz and 44.2 mhz, 44.2 mhz and 88.4 mhz, or 88.4 mhz and 176.8 mhz, the user must configure the ADN2905 to use the correct reference frequency range by setting the two bits of fref_range [1:0] ( bits [ d 5: d 4] in register 0xf ) . table 21 . ltr _mode register settings fref_ range[1:0] range (mhz) data_to_ ref_r atio[3:0] ratio 00 11.05 to 22.1 0000 2 ? 1 01 22.1 to 44.2 0001 2 0 10 44.2 to 88.4 n 2 n ? 1 11 88.4 to 176.8 1010 2 9 the user can specify a fixed integer multiple of the reference clock to lock onto using the data_to_ref_ratio [3:0] bits ( bits [ d 3: d 0] in reg i s ter 0xf ) , as follows: data_to_ref _ratio [3:0] = d ata r ate div_ f ref where div_ f ref represents the divided - d own reference referred to the 11.05 mhz to 22.1 mhz band. for example, if the reference clock frequency is 38.88 mhz and the input data rate is 622.08 mbps , the fref_range [1:0] bits are set to 01 to give a divided - down reference clock of 19.44 mhz. data_to_ref_ratio [3:0] is set to 0110, that is, 6 , because 622.08 mbps /19.44 mhz = 2 (6 ? 1) if the ADN2905 is operating in lock to reference mode, and the user changes the reference frequency, the f ref range or the f r ef ratio (bits[d5:d4] or bits[d3:d0], respectively, in register 0xf), this change must be followed by writing a low to high to low transition to the init_freq_acq bit ( bit d6 in register 0x9 ) to initiate a new lock to reference command. by default in l ock to r eference c lock mode, when lock has been achieved and the ADN2905 is in tracking mode, the frequency of the dco is compared to the frequency of the reference clock . if this frequency error exceeds 1000 ppm, lock is lost, lol is asserted , and the device relocks to the r eference c lock while continuing to output a stable clock. an alternative configuration is enabled by setting lol data ( bit d 6 in register 0xf ) to 1. in this configuration , when the device is in tracking mode, the frequency of the dco is compared to the frequency of the input data rather than the frequency of the r eference c lock. if this frequency error exceeds 1000 p pm, lock is lost, lol is asserted , and the device relocks to the r eference c lock while continuing to output a stable clock . using the reference clock to measure data frequency the user can also provide a reference clock to measure the recovered data freque ncy. in this case, the user provides a reference clock, and the ADN2905 compares the frequency of the incoming data to the incomin g reference clock and returns a ratio of the two frequencies to 0.01% (100 ppm). the accuracy error of the reference clock is added to the accuracy error of the ADN2905 data rate measurement. for example, if a 100 ppm accuracy reference clock is used, the total accuracy of the measurement is 200 ppm. the reference clock can range from 11.05 mhz and 176.8 mhz . prior to reading back th e data rate using the reference clock, the fref_range[1:0] bits (bits[d5:d4] in register 0xf) must be set to the appropriate frequency range with respect to the reference clock being used according to table 21 .
ADN2905 data sheet rev. a | page 22 of 27 a fine data rate r eadback is then executed as follows: 1. apply the reference clock. 2. write a 0 to the refclk_pdn bit ( bit d2 in register 0xa ) to enable the reference clock circuit. 3. write to the fref_range [1:0] bits ( bits [ d 5: d 4] in register 0xf ) to select the appropriate referen ce clock frequency circuit. 4. write a 1 to the rate_meas_en bit ( bit d 1 in register 0x8 ) to enable the fine data rate measure ment capability of the ADN2905 . this bit is level sensitive and does not need to be reset to perform subsequent frequency measurements. 5. write a low to high to low transition to the rate_meas_ reset bit ( bit d0 in register 0x8 ) to initiate a new data rate measurem ent. 6. read back the rate_meas_comp bit ( bit d 0 in register 0x6 ) . if the bit is 0, the measurement is not complete. if it is 1, the measurement is complete and the data rate can b e read back on the rate_freq[23:0] and freq_rb2[6 :2 ] bits (see table 7 ) . the approximate time for a data rate measurement is given in equation 2 . use the following equation to determine the data rate: ( ) divrate fullrate ltr[5:4] refclk datarate f 23:0] rate_freq[ f 2 2 2 2 7 = (1) w here: f d atar at e is the data rate in mbps. r ate _ freq[23:0] is from freq2[7:0] (m ost significant b yte), freq1[7:0], and freq0[7:0] (least significant b yte). see table 7 . f refclk is the reference clock frequency in mhz. ltr[5:4] = ltr_mode[5:4] . fullrate = freq_r b2[6] ( b it d6 in register 0x5) . divrate = freq_rb 2[5:2] ( b its[d5:d2] in register 0x5) . msb lsb d23 to d16 d15 to d8 d7 to d0 freq2[7:0] freq1[7:0] freq0[7:0] consider the example of a 1.25 gbps (ge) input signal and a reference clock source of 32 mhz at the pin/nin and refclkp/ refclkn ports , respect ively. in this case, the fref_ range [1:0] bits ( bits[d5:d4] in register 0xf ) are 01, and the reference frequency falls into the range of 22.1 mhz to 44.2 mhz . after following step 1 throu gh step 6 , the read back value of the rate_freq[2 3 :0] bits is 0x13880, which is equal to 8 10 4 . the re ad back value of the fullrate bit ( bit d6 in register 0x5 ) is 1 , and the read back value of the divrate[3:0] bits ( bits[d5:d2] in register 0x5 ) is 2. inserting these values into equation 1 yields ((8 10 4 ) (32 10 6 ))/(2 1 2 7 2 1 2 2 ) = 1.25 gbps if subsequent frequency measurements are required, keep the rate_meas_en bit ( bit d 1 in register 0x8 ) set to 1. it does not need to be reset. the measurement process is reset by writing a 1 followed by a 0 to the rate_meas_rese t bit ( bit d 0 in register 0x8 ) . this initiates a new data rate measurement. follow step 2 through step 6 to read back the new data rate. note that a data rate readback is valid only if the lol pin is low. if lol is high, the data rate readback is invalid. initiating a frequency measurement by writing a low to high to low transition to the rate_meas_reset bit ( bit d 0 in register 0x8 ) also resets the rate_meas_comp bit ( bit d 1 0 in register 0x 6 ) . the approximate time to complete a frequency measurement from th e rate_meas_reset bit being written with a low to high to low transition to when the rate_meas_comp bit returns high is given by measurement time = refclk ltr[5:4] f 2 2 11 (2) additional features available v ia the i 2 c interface coarse data rate readback th e data rate can be read back over the i 2 c interface to approx - imately 5 % without using an external reference clock according t o the following formula: data rate = divrate fullrate dco f 2 2 (3 ) where f dco is the frequency of the dco, derived as shown in table 22. fullrate = freq_rb2[6] (bit d6 in register 0x5) . divrate = freq_rb2[5:2] (bits[d5:d2] in register 0x5) . four oscillator cores , defined by the vcosel[9:8] bits ( bits[d 1: d 0] in register 0x5 ) , span the highest octave of data ra tes according to table 22. table 22 . dco center frequency vs. vcosel[9:8] core = ( vcosel[9:8] ) min imum frequency (mhz) = m in _ f ( c ore) max imum frequency (mhz) = m ax _ f ( c ore) 0 5570 7105 1 7000 8 685 2 861 0 10,3 30 3 10,2 65 11, 625 determine f dco from the vcosel[9:0] bits (bits[d7:d0] in register 0x4, and bits[d1:d0] in register 0x5) , using the following formula: ] vcosel[9:0 core f min core f max core f min f dco ? + = 256 ) ( _ ) ( _ ) ( _ (4)
data sheet ADN2905 rev. a | page 23 of 27 wor k e d example read back the contents of the freq_rb1 and freq_rb2 registers . for example, with a cpri 16 ( 9.8304 gbps ) signal presented to the pin/nin ports freq_rb1 = 0x ba freq_rb2 = 0x02 fullrate ( freq_rb2[ 6 ]) = 0 divrate ( freq_rb2[5:2]) = 0 c ore ( freq_rb2[1:0]) = 2 then f dco = mbps 89 . 9837 186 256 mbps 8610 mbps 300 , 10 mbps 8610 = ? + and gbps 83789 . 9 2 2 mbps 89 . 9837 0 0 = = data f initiate frequency acquisition a frequency acquisition can be initiated by writing a 1 followed by a 0 to the init_freq_acq bit ( bit d 6 in register 0x9 ) . this initiates a new frequency acquisition while keeping the ADN2905 in the operating mode that was previously programmed in the ctrla, ctrlb, and ctrlc registers. prbs generator/receiver the ADN2905 has an integrated prbs generator and detector for system testing purposes. the devices are configurable as either a prbs detector or a prbs generato r. the following ste ps configure the prbs detector: 1. set the data_receiver_enable bit ( bit d2 in register 0x3f ) to 1 while also setting the data_receiver_ mode[ 1:0] bits ( bits[d1:d0] in register 0x3f ] ) according to the desired prbs pattern ( 0 = prbs7; 1 = prbs15; 2 = prbs 31 ) . setting the data_receiver_mode [1:0] bits to 3 leads to a one shot sampling of recovered data into the data_loaded [15:0] bits . 2. set the data_receiver_clear bit ( bit d 3 in register 0x3f ) to 1 followed by 0 to clear the prbs_error and prb s _error_count bits . 3. the s tates of the prbs _ error bit ( bit d0 in register 0x41 ) and the prbs _ error_count [7:0] bits ( bits [ d 7: d 0] in register 0x40 ) can be frozen by setting the data_ receiver_enable bits ( bit d 2 in register 0x3f ) to 0. the following steps co nfigure the prbs generator : 1. set the data_gen_en bit ( bit d2 in register 0x39 ) to 1 to enabl e the prbs generator and set the data_gen_ mode [1:0] bits ( bits[d1:d0] in register 0x39 ) for the desired prbs output pattern ( 0 = prbs7; 1 = prb s15; 2 = prbs 31 ) . an arbitrary 32 - bit pattern stored as prog_ data [31: 0] is activated by setting the data_gen_ mode [1:0] bits to 3. 2. s trings of consecutive identical digits (cids) sense d from the data_cid_bit bit ( bit d5 in register 0x39 ) can be introduced in the generator by setting the data_cid_en bit ( bit d4 in register 0x39 ) to 1. the length of cids is 8 data_cid_length , which is set via bits [ d 7: d 0] in register 0x3a . table 23. prbs settings prbs pattern data_e_mode [1:0] prbs polynomial prbs 7 0x 00 1 + x 6 + x 7 prbs15 0x01 1 + x 14 + x 15 prbs31 0x10 1 + x 28 + x 31 prog_data [31:0] 0x11 n/a double data rate mode the default output clock mode is a d ouble d ata r ate (ddr) clock, where the output clock frequency is ? the data rate. ddr mode allows dire ct interfacing to fpgas that support clocking on both rising and falling edges. setting the ddr_ disable bit ( bit d 2 in register 0x1e ) to 1 enables full data rate mode. full data rate mode is not supported for data rates in the highest octave between 5.6 gb ps and 9.8304 g bps . cdr bypass mode the cdr in the ADN2905 can be bypassed by setting the cdr bypass bit ( bit d5 in register 0x9 ) to 1. in this mode, the ADN2905 feeds the input directly through the input amplifiers to the output buffer, bypassing the cdr. th e cdr b ypass path is intended for use in testing or debugging a system. use the cdr bypass path at data rates at or below 3.0 gb p s only . transmission lines use of 50 transmission lines is required for all high frequency input and output signals to minim ize reflections: pin, nin, datout p, and datout n (also refclkp and refclkn, if using a high frequency reference clock, such as 155 mhz). it is also necessary for the pin and nin input traces to be matched in length, and the datout p and datout n output traces to be matched in length to avoid skew between the differential traces. the high speed inputs (pin and nin) are each internally termi - nat ed with 50 to an internal reference voltage (see figure 26) . as with any high speed , mixed - signal circuit , take care to keep all high speed digital traces away from sensitive analog nodes. the high speed outputs ( datout p, datout n ) are int ernally terminated with 50 to vcc. soldering guidelines for lead frame chip scale package the lands on the 24 - lead lfcsp are rectangular. the printed circuit board pad for these is 0.1 mm longer than the package land length, and 0.05 mm wider than the package land width. center the land on the pad to ensure that the solder joint size is maximized. the bottom of the lead frame chip scale package has a central exposed pad. the pad on the printed circuit board must be at least as large as this exposed pad. c onnect the exposed pad to vee using plugged vias to prevent solder from leaking
ADN2905 data sheet rev. a | page 24 of 27 through the vias during reflow. this ensures a solid connection from the exposed pad to vee. it is highly recommended to include as many vias as possible when connecting the exposed pad to vee. this minimize s the thermal resistance between the die and vee, and minimize s the die temp erature . it is recommended that the vias be connect ed to a vee plane, or planes, rather than a signal trace to improve heat dissipation , as shown in figure 23. placing an external vee plane on the backside of the board opposite the ADN2905 provides an additional benefit because this allows easier heat dissipation into the ambient environment. input configurations the ADN2905 input stage can work with the signal source in an ac - coupled or dc - coupled configuration. to best fit in a required applications environment, the ADN2905 supports one of following inpu t modes: equalizer, or bypass. t he ADN2905 can be configured to use any re quired input configuration through the i 2 c bus. figure 22 shows a block diagram of the input stage circuit. 0db eq vcc float v ref input_sel[1:0] rx_term_float eq pin nin 2 50? 50? 2.9k? 2.9k? 12624-022 figure 22 . input stage block diagram the input signal pa th is configurable with the input_ sel [1 :0] bits ( bits[d 6: d 5] in register 0x16 ) . table 24 shows the input_ sel [1:0] bits and the input signal configuration. table 24 . input signal confi guration selected input input_sel[1:0] rx_term_float = 0 rx _term_float = 1 ADN2905 availability limiting amplifier 0 0 v ref not defined not defined equalizer 0 1 v ref not defined yes 0 db eq 10 vcc float y es not defined 11 not defined not defined not defined 12624-023 figure 23 . connecting vias to vee
data sheet ADN2905 rev. a | page 25 of 27 choosing ac coupling capacitors ac coupling capacitors at the input s (pin, nin) and output s ( datout p, datout n) of the ADN2905 must be chosen such that the device works properly over the full range of data rates used in the application. when choosi ng the capacitors, the time constant formed with the two 50 resistors in the signal path must be considered. when a large number of consecutive iden tical digits (cids) are applied, the capacitor voltage can droop due to baseline wander (see figure 24 ), causing pattern dependent jitter (pdj). the user must determine how much droop is tolerable and choose an ac coupling capacitor based on that amount of droop. the amount of pdj can then be approximated based on the capaci - tor sel ection. the actual capacitor value selection may require some trade - offs between droop and pdj. for example, assuming that 2% droop is tolerable , the maximum differential droop is 4%. normalizing to v p - p, droop = v = 0.04 v = 0.5 v p - p (1 ? e ? t/ ) t herefore, = 12 t where: is the rc time constant (c is the ac coupling capacitor, r = 100 seen by c). t is the total discharge time . t = n where: n is the number of cids. t is the bit period. calculate the capacitor value by combining the equations for and t . c = 12 nt / r when the capacitor value is selected, the pdj can be approximated as pdj ps p - p = 0.5 t r (1 ? e (?nt/rc ) /0.6 where: pdj ps p - p is the amount of pattern dependent jitter allowed , <0.01 u i p - p typical. t r is the rise time, which is equal to 0.22/ bw ; bw 0.7 (bit rate). n ote that this expression for t r is accurate only for the inputs. the output rise time for the ADN2905 is ~30 ps regardless of data rate. notes 1. during the data patterns with high transition density, differential dc voltage at v1 and v2 is zero. 2. when the tia outputs consecutive identical digits, v1 and v1b are driven to different dc levels. v2 and v2b discharge to the v ref level, which effectively introduces a differential dc offset across the ac coupling capacitors. 3. when the burst of data starts again, the differential dc offset across the ac coupling capacitors is applied to the input levels, causing a dc shift in the differential input. this shift is large enough that one of the states, either high or low, depending on the levels of v1 and v1b when the tia went to cid, is cancelled out. the quantizer does not recognize this as a valid state. 4. the dc offset slowly discharges until the differential input voltage exceeds the sensitivity of the ADN2905. the quantizer recognizes both high and low states at this point. v1 v1b v2 v2b vdiff vdiff = v2 ? v2b vth = ADN2905 quantizer threshold 2 3 4 1 v ref vth cdr v ref 50? 50? pin nin ADN2905 c out dataoutp dataoutn c in v2 v2b v1 v1b tia vcc 2 12624-024 figure 24 . example of baseline wander
ADN2905 data sheet rev. a | page 26 of 27 dc - coupled application the inputs to the ADN2905 can also be dc - coupled. this can be necessary in burst mode applications with long periods of cids and where baseline wander cannot be tolerated . if the inputs to the ADN2905 are dc - coupled, care must be taken not to violate the input range and common - mode level requirements of the ADN2905 (see figure 28 or figure 29 ). if dc coupling is required, and the output levels of the trans impedance amplifier ( tia ) do not adhere to the levels shown in figure 28 or figure 29 , level shifting and/or attenuation must occur between the tia outputs and the ADN2905 inputs. 50? 50? 50? ADN2905 vcc ti a pin nin tia 12624-025 figure 25 . dc - coupled application , bypass input (rx term ination float mode ) figure 26 shows the defau lt dc - coupled configuration when using the b ypass input. the two term ination s are connected directly to vcc in a normal cml fashion, giving a common mode that is set by the dc signal strength from the driving chip. the b ypass input has a high common - mode r ange and can tolerate v cm up to and including vcc. 50? 50? 50? vcc ADN2905 pin i nin 12624-026 figure 26 . dc - coupled application, bypass input (normal mode) 50? 50? 50? 50? 50? vcc vcc ADN2905 pin i nin 12624-027 figure 27 . dc - coupled application, bypass input ( back terminated mode) 1.2v 0.9v 600mv p-p, diff 600mv p-p, diff v cm = 1.05v v cm = 0.65v input (v) 0.8v 0.5v 12624-028 figure 28 . minimum allowed dc - coupled input levels 1.2v 0.7v 1.0v p-p, diff 1.0v p-p, diff v cm = 0.95v v cm = 0.75v input (v) 1.0v 0.5v 12624-029 figure 29 . maximum allowed dc - coupled input levels
ADN2905 data sheet outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.18 compliant to jedec standards mo-220-wggd. 03-11-2013-a bot t om view top view exposed pa d pin 1 indic at or 4.10 4.00 sq 3.90 sea ting plane 0.80 0.75 0.70 0.20 ref 0.25 min 3.16 min coplanarity 0.08 pin 1 indic at or 2.65 2.50 sq 2.45 1 24 7 12 13 18 19 6 0.05 max 0.02 nom for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 30 . 24 - lead lead frame chip scale package [lfcs p] 4 mm 4 mm body and 0.75 mm package height (cp - 24 -7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ordering q uanti ty ADN2905acpz ?40c to +85c 24- lead lfcsp cp -24 -7 490 ADN2905acpz - rl7 ?40c to +85c 24- lead lfcsp cp -24 -7 1,500 evalz - ADN2905 evaluation board 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semico nductors). rev. a | pag e 28 of 29

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